(toppers-users 4418) Re: TOPPERS/FMP(Cyclone V)の第２コアの処理速度が遅い件について

[Shinya Honda]

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===================================================================
--- arm_armcc/mpcore/mpcore_tool.h      ($B%j%S%8%g%s(B 1108)
+++ arm_armcc/mpcore/mpcore_tool.h      ($B:n6H%3%T!<(B)
@@ -75,6 +75,11 @@
        cp15_icache_invalidate = 0;
            \ } while(false)

+#define CP15_ICACHE_INVALIDATE() do {
            \+       register uint32_t cp15_branchip_invalidate
__asm("cp15:0:c7:c5:6");     \
+       cp15_branchip_invalidate = 0;
            \+} while(false)
+
 #if __TARGET_ARCH_ARM == 6

 #define CP15_DCACHE_INVALIDATE() do {
            \Index: arm_gcc/mpcore/mpcore.c
===================================================================
--- arm_gcc/mpcore/mpcore.c     (a?aa??a?$B8c(B?$B'c(B?3 1122)
+++ arm_gcc/mpcore/mpcore.c     ($Bd=(B?$Bf%-c(B?$B3c(B??a??)
@@ -477,6 +477,9 @@

        mpcore_dcache_invalidate();

+       CP15_DATA_SYNC_BARRIER();
+       CP15_PBUFFER_FLUSH();
+
        bits |= CP15_CONTROL_C_BIT;
        CP15_CONTROL_WRITE(bits);
 }
@@ -501,6 +504,9 @@
        else{
                mpcore_dcache_invalidate();
        }
+
+       CP15_DATA_SYNC_BARRIER();
+       CP15_PBUFFER_FLUSH();
 }

 /*
@@ -515,13 +521,18 @@
        /*
         *  $B$9$G$KM-8z$J$i%j%?!<%s(B
         */
-       if(bits & CP15_CONTROL_I_BIT){
+       if((bits & (CP15_CONTROL_I_BIT|CP15_CONTROL_Z_BIT))
+          == (CP15_CONTROL_I_BIT|CP15_CONTROL_Z_BIT)){
                return;
        }

        mpcore_icache_invalidate();
+       CP15_BRANCHP_INVALIDATE();

-       bits |= CP15_CONTROL_I_BIT;
+       CP15_DATA_SYNC_BARRIER();
+       CP15_PBUFFER_FLUSH();
+
+       bits |= CP15_CONTROL_I_BIT|CP15_CONTROL_Z_BIT;
        CP15_CONTROL_WRITE(bits);
 }

@@ -538,6 +549,9 @@
        CP15_CONTROL_WRITE(bits);

        mpcore_icache_invalidate();
+
+       CP15_DATA_SYNC_BARRIER();
+       CP15_PBUFFER_FLUSH();
 }

 /*
@@ -658,7 +672,7 @@
        mpcore_pbuffer_flash();

        /*
-        * TTBR0$B$rMQ$$$kMQ$K;XDj(B
+        * TTBR0$B$rMQ$$$kMM$K;XDj(B
         */
        CP15_TTBCR_WRITE(0);

Index: arm_gcc/mpcore/mpcore.h
===================================================================
--- arm_gcc/mpcore/mpcore.h     ($B%j%S%8%g%s(B 1122)
+++ arm_gcc/mpcore/mpcore.h     ($B:n6H%3%T!<(B)
@@ -61,6 +61,7 @@
 #define CP15_CONTROL_XP_BIT   (1 << 23)
 #define CP15_CONTROL_V_BIT    (1 << 13)
 #define CP15_CONTROL_I_BIT    (1 << 12)
+#define CP15_CONTROL_Z_BIT    (1 << 11)
 #define CP15_CONTROL_C_BIT    (1 <<  2)
 #define CP15_CONTROL_M_BIT    (1 <<  0)

Index: arm_gcc/mpcore/mpcore_tool.h
===================================================================
--- arm_gcc/mpcore/mpcore_tool.h        ($B%j%S%8%g%s(B 1122)
+++ arm_gcc/mpcore/mpcore_tool.h        ($B:n6H%3%T!<(B)
@@ -57,6 +57,8 @@
 #define CP15_AUXILIARY_WRITE(x)  Asm("mcr p15, 0, %0, c1, c0, 1"::"r"(x))

 #define CP15_ICACHE_INVALIDATE()           Asm("mcr p15, 0, %0, c7, c5,
0"::"r"(0))
+#define CP15_BRANCHP_INVALIDATE()          Asm("mcr p15, 0, %0, c7, c5,
6"::"r"(0))
+
 #if __TARGET_ARCH_ARM == 6
 #define CP15_DCACHE_INVALIDATE()           Asm("mcr p15, 0, %0, c7, c6,
0"::"r"(0))
 #define CP15_DCACHE_CLEAN_AND_INVALIDATE() Asm("MCR p15, 0, %0, c7,
c14, 0"::"r"(0))


On 2015/08/31 18:44, y.akiyoshi ＠ screen.co.jp wrote:
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